129 search results - page 23 / 26 » Novel Design Methodology for High-Performance XOR-XNOR Circu... |
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
We describe an efficient, top-down strategy for overlap removal and floorplan repair which repairs overlaps in floorplans produced by placement algorithms or rough floorplanni...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Modern high performance processors employ advanced techniques for thermal management, which rely on accurate readings of on-die thermal sensors. As the importance of thermal effec...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal re...