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» On Reducing Circuit Malfunctions Caused by Soft Errors
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DFT
2008
IEEE
86views VLSI» more  DFT 2008»
14 years 1 months ago
On Reducing Circuit Malfunctions Caused by Soft Errors
Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xu...
VTS
2005
IEEE
102views Hardware» more  VTS 2005»
14 years 1 months ago
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
DFT
2003
IEEE
79views VLSI» more  DFT 2003»
14 years 23 days ago
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
Kartik Mohanram, Nur A. Touba
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
14 years 1 months ago
An analytical approach for soft error rate estimation in digital circuits
—Soft errors due to cosmic rays cause reliability problems during lifetime operation of digital systems, which increase exponentially with Moore’s law. The first step in develo...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
ITC
2003
IEEE
141views Hardware» more  ITC 2003»
14 years 22 days ago
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
Kartik Mohanram, Nur A. Touba