38 search results - page 5 / 8 » On Reducing Test Data Volume and Test Application Time for M... |
ITC
2003
IEEE
14 years 24 days ago
2003
IEEE
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
ISVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...