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» On optimal input design in system identification for control
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ISCA
2003
IEEE
104views Hardware» more  ISCA 2003»
14 years 28 days ago
Token Coherence: Decoupling Performance and Correctness
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
Milo M. K. Martin, Mark D. Hill, David A. Wood
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 23 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
IJRR
2010
125views more  IJRR 2010»
13 years 5 months ago
Mechanics of Flexible Needles Robotically Steered through Soft Tissue
The tip asymmetry of a bevel-tip needle results in the needle naturally bending when it is inserted into soft tissue. This enables robotic needle steering, which can be used in me...
Sarthak Misra, Kyle B. Reed, Benjamin W. Schafer, ...
MOBISYS
2007
ACM
14 years 7 months ago
MobiSteer: using steerable beam directional antenna for vehicular network access
In this work, we investigate the use of directional antennas and beam steering techniques to improve performance of 802.11 links in the context of communication between a moving v...
Vishnu Navda, Anand Prabhu Subramanian, Kannan Dha...