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» On the Fault Testing for Reversible Circuits
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VTS
1996
IEEE
76views Hardware» more  VTS 1996»
13 years 11 months ago
Test point insertion based on path tracing
This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than us...
Nur A. Touba, Edward J. McCluskey
DAC
2003
ACM
14 years 24 days ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
ETS
2006
IEEE
119views Hardware» more  ETS 2006»
14 years 1 months ago
On-Chip Test Generation Using Linear Subspaces
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...
Ramashis Das, Igor L. Markov, John P. Hayes
DAC
2004
ACM
14 years 29 days ago
A new state assignment technique for testing and low power
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J....
ICRA
2006
IEEE
99views Robotics» more  ICRA 2006»
14 years 1 months ago
Application of Set Membership Identification for Fault Detection of MEMS
- In this article, a set membership (SM) identification technique is tailored to detect faults in microelectromechanical systems. The SM-identifier estimates an orthotope which con...
Vasso Reppa, Anthony Tzes