296 search results - page 4 / 60 » Power Estimation in Sequential Circuits |
ASPDAC
2000
ACM
14 years 14 days ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
ARVLSI
1995
IEEE
13 years 11 months ago
1995
IEEE
Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state e...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
This paper attempts to determine the capabilities of existing Redundancy Addition and Removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we ...
ICCAD
2007
IEEE
14 years 5 months ago
2007
IEEE
