41 search results - page 8 / 9 » Process variation aware clock tree routing |
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
The NETWORK-ON-CHIP (NOC) interconnection paradigm has been gaining momentum thanks to its flexibility, scalability and suitability to deep submicron technology processes. The ne...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
COMCOM
2007
13 years 7 months ago
2007
In this paper, we focus on the challenge of demand-scalable multicast routing in wireless sensor networks. Due to the ad-hoc nature of the placement of the sensor nodes as well as...