137 search results - page 5 / 28 » Process variation dimension reduction based on SVD |
ET
2002
13 years 7 months ago
2002
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
DATE
2005
IEEE
13 years 9 months ago
2005
IEEE
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
VLSI
2007
Springer
14 years 2 months ago
2007
Springer
Abstract—Analysis and verification environments for nextgeneration nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects,...
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...