135 search results - page 8 / 27 » Reducing Power Dissipation in SRAM during Test |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
ETS
2009
IEEE
13 years 5 months ago
2009
IEEE
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
ITC
2003
IEEE
14 years 27 days ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...