768 search results - page 33 / 154 » Robustness of Sequential Circuits |
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
DSD
2009
IEEE
14 years 3 months ago
2009
IEEE
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthe...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
In this paper we propose an efficient transient test generation method to comprehensively test analog circuits using minimum test time. A divide and conquer strategy is formulated...