59 search results - page 4 / 12 » Runtime leakage power estimation technique for combinational... |
CASES
2008
ACM
13 years 9 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
ISLPED
2003
ACM
14 years 22 days ago
2003
ACM
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...