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» Scale in Chip Interconnect requires Network Technology
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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 5 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
14 years 1 months ago
A methodology for the characterization of process variation in NoC links
—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that...
Carles Hernandez, Federico Silla, José Duat...
NOCS
2007
IEEE
14 years 2 months ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston
PPL
2008
185views more  PPL 2008»
13 years 8 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ASAP
2003
IEEE
108views Hardware» more  ASAP 2003»
14 years 1 months ago
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
Terry Tao Ye, Giovanni De Micheli