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VLSID
2004
IEEE
93views VLSI» more  VLSID 2004»
14 years 9 months ago
Random Access Scan: A solution to test power, test data volume and test time
Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
VLSID
2002
IEEE
82views VLSI» more  VLSID 2002»
14 years 9 months ago
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Raj...
DAC
1989
ACM
14 years 18 days ago
Special Purpose Architecture for Accelerating Bitmap DRC
In this paper we propose algorithms for performing DRC on a bitmapped layout altd developspecial purpose architecture for its implementation. we Use window scan method, with flexib...
Narasimha B. Bhat, S. K. Nandy
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 9 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...