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TCAD
1998
82views more  TCAD 1998»
13 years 7 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
DATE
2009
IEEE
123views Hardware» more  DATE 2009»
13 years 11 months ago
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...
ICCAD
1996
IEEE
81views Hardware» more  ICCAD 1996»
13 years 11 months ago
Logic optimization by output phase assignment in dynamic logic synthesis
Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser
ARITH
2009
IEEE
14 years 2 months ago
Challenges in Automatic Optimization of Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, espec...
Ajay K. Verma, Philip Brisk, Paolo Ienne