376 search results - page 35 / 76 » Self-Assembled Circuit Patterns |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a hybrid BIST approach that extracts the most frequently occurring sequences from deterministic test patterns; these extracted sequences are stored on-chip. We use clus...
ITC
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
MEMOCODE
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The s...
ICRA
2005
IEEE
14 years 1 months ago
2005
IEEE
– We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordina...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...