As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
Thomas D. Richardson, Chrysostomos Nicopoulos, Don...
We propose two crosstalk reducing coding schemes using ternary busses. In addition to low power consumption and reduced delay, our schemes offer other advantages over binary codin...