155 search results - page 3 / 31 » Soft delay error analysis in logic circuits |
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—The Delay Filtered Dual Interlocked storage Cell (DF-DICE) offers a scalable solution in different radiation environments for soft error mitigation. The area and speed performan...
DFT
2003
IEEE
14 years 29 days ago
2003
IEEE
A new methodology for designing logic circuits with partial error masking is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic cir...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
ISQED
2010
IEEE
14 years 23 days ago
2010
IEEE
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
IOLTS
2008
IEEE
14 years 2 months ago
2008
IEEE
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...