155 search results - page 4 / 31 » Soft delay error analysis in logic circuits |
ITC
2003
IEEE
14 years 28 days ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of th...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), ...
PATMOS
2007
Springer
14 years 1 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...