87 search results - page 1 / 18 » Space of DRAM fault models and corresponding testing |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract: DRAMs play an important role in the semiconductor industry, due to their highly dense layout and their low price per bit. This paper presents the first framework of faul...
DDECS
2009
IEEE
13 years 11 months ago
2009
IEEE
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
DATE
2002
IEEE
14 years 9 days ago
2002
IEEE
: It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible...
VTS
2000
IEEE
13 years 11 months ago
2000
IEEE
Abstract: This paper presents a notation for describing functional fault models, which may occur in memory devices. Using this notation, the space of all possible memory faults has...