306 search results - page 21 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
TCS
2008
13 years 8 months ago
2008
Starting from the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach based on timed automata. We obtain a refined ...