This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exc...
Matthew R. Guthaus, Natesan Venkateswaran, Vladimi...
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
As the scale of system integration continues to grow, the on-chip communication becomes the ultimate bottleneck of system performance and the primary determinant of system archite...
Starting from the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach based on timed automata. We obtain a refined ...