246 search results - page 21 / 50 » Statistical gate sizing for timing yield optimization |
ICCAD
1997
IEEE
13 years 12 months ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
USS
2008
13 years 10 months ago
2008
We address the problem of auditing an election when precincts may have different sizes. Prior work in this field has emphasized the simpler case when all precincts have the same s...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modu...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...