246 search results - page 22 / 50 » Statistical gate sizing for timing yield optimization |
IPPS
2000
IEEE
14 years 20 hour ago
2000
IEEE
We consider technology mapping from factored form binary leaf-DAG to lookup tables LUTs , such as those found in eld programmable gate arrays. Polynomial time algorithms exist f...
VLSID
2006
IEEE
14 years 8 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
ct Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particul...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
ICCAD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...