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ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 6 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
14 years 6 months ago
A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devi
—In this paper, we present an approach to nonlinear model reduction based on representing a nonlinear system with a piecewise-linear system and then reducing each of the pieces w...
Michal Rewienski, Jacob White
ASPDAC
1998
ACM
65views Hardware» more  ASPDAC 1998»
14 years 2 months ago
A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
Miyako Tandai, Takao Shinsha
ICCAD
2002
IEEE
126views Hardware» more  ICCAD 2002»
14 years 2 months ago
Robust and passive model order reduction for circuits containing susceptance elements
Numerous approaches have been proposed to address the overwhelming modeling problems that result from the emergence of magnetic coupling as a dominant performance factor for ICs a...
Hui Zheng, Lawrence T. Pileggi
ASPDAC
2007
ACM
81views Hardware» more  ASPDAC 2007»
14 years 1 months ago
Fault Dictionary Size Reduction for Million-Gate Large Circuits
- In general, fault dictionary is prevented from practical applications for its extremely large size. Several previous works are proposed for the fault dictionary size reduction. H...
Yu-Ru Hong, Juinn-Dar Huang