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» Structural In-Field Diagnosis for Random Logic Circuits
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DAC
2005
ACM
14 years 8 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
14 years 1 months ago
Automated Testability Enhancements for Logic Brick Libraries
Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT ...
Jason G. Brown, Brian Taylor, Ronald D. Blanton, L...
KR
2000
Springer
13 years 11 months ago
Anytime Diagnostic Reasoning using Approximate Boolean Constraint Propagation
In contrast with classical reasoning, where a solution is either correct or incorrect, approximate reasoning tries to compute solutions which are close to the ideal solution, with...
Alan Verberne, Frank van Harmelen, Annette ten Tei...
ATS
2003
IEEE
110views Hardware» more  ATS 2003»
14 years 23 days ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang
VLSID
2006
IEEE
129views VLSI» more  VLSID 2006»
14 years 7 months ago
A Stimulus-Free Probabilistic Model for Single-Event-Upset Sensitivity
With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a ...
Mohammad Gh. Mohammad, Laila Terkawi, Muna Albasma...