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DATE
2004
IEEE
152views Hardware» more  DATE 2004»
14 years 1 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
DATE
1997
IEEE
95views Hardware» more  DATE 1997»
14 years 2 months ago
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
14 years 2 months ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
DSD
2006
IEEE
93views Hardware» more  DSD 2006»
14 years 3 months ago
High-Level Decision Diagram based Fault Models for Targeting FSMs
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
Jaan Raik, Raimund Ubar, Taavi Viilukas
ICCAD
2003
IEEE
190views Hardware» more  ICCAD 2003»
14 years 6 months ago
IDAP: A Tool for High Level Power Estimation of Custom Array Structures
—While array structures are a significant source of power dissipation, there is a lack of accurate high-level power estimators that account for varying array circuit implementat...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...