60 search results - page 7 / 12 » System level clock tree synthesis for power optimization |
ISLPED
2003
ACM
13 years 12 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ICCAD
2000
IEEE
13 years 11 months ago
2000
IEEE
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic ...
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
CORR
2008
Springer
13 years 6 months ago
2008
Springer
Mobile devices, like sensor networks and MEMS actuators use mobile power supplies to ensure energy for their operation. These are mostly batteries. The lifetime of the devices dep...
VLSID
2006
IEEE
14 years 21 days ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...