1016 search results - page 7 / 204 » Test Generation for Designs with On-Chip Clock Generators |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
ASPDAC
2000
ACM
13 years 12 months ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
ITC
1998
IEEE
13 years 12 months ago
1998
IEEE
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...