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» Test generation in VLSI circuits for crosstalk noise
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VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
14 years 8 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...
ASPDAC
2005
ACM
107views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Constraint extraction for pseudo-functional scan-based delay testing
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Chen...
VLSID
1997
IEEE
399views VLSI» more  VLSID 1997»
13 years 12 months ago
A Self-Biased High Performance Folded Cascode CMOS Op-Amp
Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptiblity of the bias lines to noise...
Pradip Mandal, V. Visvanathan
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 27 days ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
13 years 11 months ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...