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» The ISPD98 circuit benchmark suite
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ISLPED
1997
ACM
96views Hardware» more  ISLPED 1997»
14 years 3 months ago
Re-mapping for low power under tight timing constraints
In this paper1 we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algo...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
DAC
2006
ACM
14 years 11 months ago
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...
Ashish Kumar Singh, Murari Mani, Ruchir Puri, Mich...
ASPDAC
2004
ACM
141views Hardware» more  ASPDAC 2004»
14 years 4 months ago
An approach for reducing dynamic power consumption in synchronous sequential digital designs
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
Noureddine Chabini, Wayne Wolf
DAC
2008
ACM
14 years 12 months ago
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation
ng Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation Yan Chen Dept. of Computer Science Portland State University Portland, OR, 97207 chenyan@cs.pdx.e...
Yan Chen, Fei Xie, Jin Yang
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 11 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...