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» The Validity of Retiming Sequential Circuits
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ISQED
2009
IEEE
133views Hardware» more  ISQED 2009»
14 years 2 months ago
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue o...
Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsi...
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 4 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
MICRO
2006
IEEE
159views Hardware» more  MICRO 2006»
13 years 7 months ago
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ICCD
2006
IEEE
127views Hardware» more  ICCD 2006»
14 years 4 months ago
Power Droop Testing
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...
Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd...
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 2 months ago
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...
Andrea Calimera, Luca Benini, Enrico Macii