26 search results - page 3 / 6 » Thermal via placement in 3D ICs |
DAC
2012
ACM
11 years 11 months ago
2012
ACM
In this paper, we propose two methods used in 3D IC placement that effectively exploit the die-to-die thermal coupling in the stack. First, TSVs are spread on each die to reduce t...
DAC
2011
ACM
12 years 8 months ago
2011
ACM
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
Heat dissipation is one of the most serious challenges in 3D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias....
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via lo...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...