6111 search results - page 167 / 1223 » Time, Hardware, and Uniformity |
DATE
2002
IEEE
14 years 3 months ago
2002
IEEE
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
A new method for computation of timing jitter in a PLL is proposed. The computational method is based on the representation of the circuit as a linear time-varying system with mod...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
Capacitance coupling can have a significant impact on gate delay in today's deep submicron circuits. In this paper we present a static timing analysis tool that calculates th...
ICCAD
2000
IEEE
14 years 2 months ago
2000
IEEE
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and the...