264 search results - page 14 / 53 » Timing driven power gating |
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
— In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nan...
ASAP
2007
IEEE
13 years 10 months ago
2007
IEEE
This paper explores the reliability of three different minimum fan-in majority gates full adder (FA) designs, and compares them to the performance of a standard XOR-based FA. The ...
ISSS
1999
IEEE
14 years 27 days ago
1999
IEEE
The policy optimization problem for dynamic power management has received considerable attention in the recent past. We formulate policy optimization as a constrained optimization...
CODES
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
ISPD
2009
ACM
14 years 3 months ago
2009
ACM
Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven h...