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» Timing-driven optimization using lookahead logic circuits
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ICCAD
2002
IEEE
189views Hardware» more  ICCAD 2002»
14 years 3 months ago
Reversible logic circuit synthesis
Reversible, or information-lossless, circuits have applications in digital signal processing, communication, computer graphics and cryptography. They are also a fundamental requir...
Vivek V. Shende, Aditya K. Prasad, Igor L. Markov,...
DAC
2003
ACM
14 years 8 days ago
Force directed mongrel with physical net constraints
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna P...
CSREAESA
2003
13 years 8 months ago
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
14 years 1 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
ICCAD
2008
IEEE
117views Hardware» more  ICCAD 2008»
14 years 1 months ago
A novel sequential circuit optimization with clock gating logic
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang