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DAC
2009
ACM
14 years 8 months ago
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
Shiyan Hu, Zhuo Li, Charles J. Alpert
ISPD
2009
ACM
141views Hardware» more  ISPD 2009»
14 years 2 months ago
A faster approximation scheme for timing driven minimum cost layer assignment
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
Shiyan Hu, Zhuo Li, Charles J. Alpert
FPL
2003
Springer
113views Hardware» more  FPL 2003»
14 years 27 days ago
Data Dependent Circuit Design: A Case Study
Abstract. Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and...
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
13 years 11 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
ICSM
1999
IEEE
13 years 12 months ago
A Two-Phase Process for Software Architecture Improvement
Software architecture is important for large systems in which it is the main means for, among other things, controlling complexity. Current ideas on software architectures were no...
René L. Krikhaar, André Postma, M. P...