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DATE
2006
IEEE
122views Hardware» more  DATE 2006»
14 years 2 months ago
Power analysis of mobile 3D graphics
— The world of 3D graphics, until recently restricted to high-end workstations and game consoles, is rapidly expanding into the domain of mobile platforms such as cellular phones...
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 1 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 3 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ICCAD
2010
IEEE
148views Hardware» more  ICCAD 2010»
13 years 6 months ago
Trace signal selection to enhance timing and logic visibility in post-silicon validation
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-s...
Hamid Shojaei, Azadeh Davoodi
ISCAS
2008
IEEE
170views Hardware» more  ISCAS 2008»
14 years 3 months ago
Integrated circuit implementation of a cortical neuron
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
Jayawan H. B. Wijekoon, Piotr Dudek