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» Use of local biasing in designing analog integrated circuits
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ASPDAC
1998
ACM
97views Hardware» more  ASPDAC 1998»
13 years 12 months ago
A Novel Design Assistant for Analog Circuits
 This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer d...
Markus Wolf, Ulrich Kleine, Frédéric...
ICCAD
2004
IEEE
80views Hardware» more  ICCAD 2004»
14 years 4 months ago
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the res...
Jintae Kim, Jaeseo Lee, Lieven Vandenberghe
DATE
2002
IEEE
151views Hardware» more  DATE 2002»
14 years 18 days ago
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets
In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets. These set...
Robert Schwencker, Frank Schenkel, Michael Pronath...
ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
14 years 4 months ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
14 years 4 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...