226 search results - page 4 / 46 » Variation-tolerant circuits: circuit solutions and technique... |
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post
DFT
2003
IEEE
14 years 19 days ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
EH
2004
IEEE
13 years 11 months ago
2004
IEEE
Multi Expression Programming (MEP) is a Genetic Programming (GP) variant that uses linear chromosomes for solution encoding. A unique MEP feature is its ability of encoding multipl...
ISPD
1999
ACM
13 years 11 months ago
1999
ACM
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...