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» Verifying VLSI Circuits
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VLSID
2004
IEEE
111views VLSI» more  VLSID 2004»
14 years 10 months ago
On Buffering Schemes for Long Multi-Layer Nets
We consider the problem of minimizing the delay in signal transmission over point-to-point connections across multiple metal layers in a VLSI circuit. We present an exact solution...
Vani Prasad, Madhav P. Desai
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
14 years 10 months ago
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
14 years 7 months ago
Multigrid-Like Technique for Power Grid Analysis
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 4 months ago
Redundant wire insertion for yield improvement
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
Jin-Tai Yan, Zhi-Wei Chen
GLVLSI
2008
IEEE
128views VLSI» more  GLVLSI 2008»
14 years 4 months ago
NBTI-aware flip-flop characterization and design
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
Hamed Abrishami, Safar Hatami, Behnam Amelifard, M...