564 search results - page 54 / 113 » Wireplanning in logic synthesis |
CDC
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract-- We present a computational framework for automatic synthesis of a feedback control strategy for a piecewise affine (PWA) system from a specification given as a Linear Te...
GLVLSI
2011
IEEE
13 years 7 days ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
Polynomial expressions are used to compute a wide variety of mathematical functions commonly found in signal processing and graphics applications, which provide good opportunities...