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VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 11 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
VLSID
2001
IEEE
88views VLSI» more  VLSID 2001»
14 years 11 months ago
Switching Noise Analysis Framework For High Speed Logic Families
Marco Delaurenti, Mariagrazia Graziano, Guido Mase...
VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
14 years 11 months ago
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, H...
VLSID
2001
IEEE
98views VLSI» more  VLSID 2001»
14 years 11 months ago
Complexity Of Minimum-Delay Gate Resizing
Supratik Chakraborty, Rajeev Murgai
VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
14 years 11 months ago
High Level Synthesis Of Multi-Precision Data Flow Graphs
Vikas Agrawal, Anand Pande, Mahesh Mehendale
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 11 months ago
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Ku...
VLSID
2002
IEEE
87views VLSI» more  VLSID 2002»
14 years 11 months ago
Simultaneous Circuit Transformation and Routing
In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire recon...
Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahi...
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
14 years 11 months ago
IEEE 1394a_2000 Physical Layer ASIC
CN4011A is IEEE 1394a_2000 standard Compliant Physical Layer ASIC. It is a 0.18um mixed-signal ASIC incorporating three analog ports, PLL, reference generator for analog along wit...
Ranjit Yashwante, Bhalchandra Jahagirdar
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
14 years 11 months ago
Efficient Macromodeling for On-Chip Interconnects
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
Qinwei Xu, Pinaki Mazumder
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
14 years 11 months ago
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun...