Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require ...
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
The fabless model was traditionally enabled through clean interfaces – both in technical and business terms – between foundries and fabless semiconductor companies. However, w...
Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulse...
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Ami...
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
Orthogonal Frequency Division Multiplexing (OFDM) is the modulation of choice for broadband wireless communications. Unfortunately, it comes at the cost of a very low energy effic...
We present a novel application for carbon nanotube devices, implementing a high density 3-D capacitor, which can be useful for decoupling applications to reduce supply voltage var...
Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal...
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...