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SBACPAD
2006
IEEE
81views Hardware» more  SBACPAD 2006»
14 years 5 months ago
Scalable Value-Cache Based Compression Schemes for Multiprocessors
Martin Thuresson, Per Stenström
SBACPAD
2006
IEEE
102views Hardware» more  SBACPAD 2006»
14 years 5 months ago
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
14 years 5 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
HPCA
2006
IEEE
14 years 5 months ago
Speculative synchronization and thread management for fine granularity threads
Performance of multithreaded programs is heavily influenced by the latencies of the thread management and synchronization operations. Improving these latencies becomes especially...
Alex Gontmakher, Avi Mendelson, Assaf Schuster, Gr...
HPCA
2006
IEEE
14 years 5 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
14 years 5 months ago
Embedded Support Vector Machine : Architectural Enhancements and Evaluation
In recent years, research and development in the field of machine learning and classification techniques have gained paramount importance. The future generation of intelligent e...
Soumyajit Dey, Monu Kedia, Niket Agarwal, Anupam B...
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
14 years 5 months ago
A Placement Methodology for Robust Clocking
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
Ganesh Venkataraman, Jiang Hu
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 5 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
VLSID
2007
IEEE
142views VLSI» more  VLSID 2007»
14 years 5 months ago
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...