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DAC
2006
ACM
14 years 5 months ago
Tomorrow's analog: just dead or just different?
This panel discusses the following topics. With the ongoing trend towards more and more digitization in applications ranging from multimedia to telecommunications, there is a big ...
Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien ...
DAC
2006
ACM
14 years 5 months ago
Electronics beyond nano-scale CMOS
This paper presents nano-scale CMOS outlook, discusses the three tenets that have made electronics successful in the past, and using these tenets conclude that there is nothing on...
Shekhar Borkar
DAC
2006
ACM
14 years 5 months ago
Building a verification test plan: trading brute force for finesse
J. Bergeron, H. Foster, A. Piziali, R. S. Mitra, C...
DAC
2006
ACM
14 years 5 months ago
Design in reliability for communication designs
Silicon design implementation has become increasingly complex with the deep submicron technologies such as 90nm and below. It is common to see multiple processor cores, several ty...
Uday Reddy Bandi, Murty Dasaka, Pavan K. Kumar
DAC
2006
ACM
14 years 5 months ago
Circuits for energy harvesting sensor signal processing
duce system weight and volume, increase operating lifetime, The recent explosion in capability of embedded and portable decrease maintenance costs, and open new frontiers for inele...
Rajeevan Amirtharajah, Justin Wenck, Jamie Collier...
DAC
2006
ACM
14 years 5 months ago
A reconfigurable design-for-debug infrastructure for SoCs
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric insert...
Miron Abramovici, Paul Bradley, Kumar N. Dwarakana...
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
14 years 5 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
14 years 5 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
14 years 5 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra