Sciweavers

HPCA
2007
IEEE
14 years 6 months ago
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
Liqun Cheng, John B. Carter, Donglai Dai
HPCA
2007
IEEE
14 years 6 months ago
Optical Interconnect Opportunities for Future Server Memory Systems
This paper deals with alternative server memory architecture options in multicore CPU generations using optically-attached memory systems. Thanks to its large bandwidth-distance p...
Y. Katayama, A. Okazaki
HPCA
2007
IEEE
14 years 6 months ago
Perturbation-based Fault Screening
Fault screeners are a new breed of fault identification technique that can probabilistically detect if a transient fault has affected the state of a processor. We demonstrate that...
Paul Racunas, Kypros Constantinides, Srilatha Mann...
HPCA
2007
IEEE
14 years 6 months ago
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
Haakon Dybdahl, Per Stenström
HPCA
2007
IEEE
14 years 6 months ago
Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
Albert Meixner, Daniel J. Sorin
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
14 years 6 months ago
Implementing the Best Processor Cores
It is well-known that varying architectural, technological and implementation aspects of embedded microprocessors, such as ARM, can produce widely differing performance and power ...
Vamsi Boppana, Rahoul Varma, S. Balajee
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
14 years 6 months ago
Testing Flash Memories for Tunnel Oxide Defects
— Testing non volatile memories for tunnel oxide defects is one of the most important aspects to guarantee cell reliability. Defective tunnel oxide layer in core memory cells can...
Mohammad Gh. Mohammad, Kewal K. Saluja
VLSID
2008
IEEE
191views VLSI» more  VLSID 2008»
14 years 6 months ago
Programming and Performance Modelling of Automotive ECU Networks
The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementa...
Samarjit Chakraborty, Sethu Ramesh
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 6 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
VLSID
2008
IEEE
93views VLSI» more  VLSID 2008»
14 years 6 months ago
Watermarking Video Clips with Workload Information for DVS
We present a lightweight scheme for watermarking or annotating video clips with information describing the workload that would be incurred while decoding the clip. This informatio...
Yicheng Huang, Samarjit Chakraborty, Ye Wang