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21

GLVLSI
1996
IEEE

102views VLSI» more GLVLSI 1996»

FPGA-based high performance page layout segmentation

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FPGA-based high performance page layout segmentation

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Nalini K. Ratha, Anil K. Jain, Diane T. Rover

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31

GLVLSI
1996
IEEE

103views VLSI» more GLVLSI 1996»

A Parametrical Architecture for Reed-Solomon Decoders

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A Parametrical Architecture for Reed-Solomon Decoders

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Mariana-Eugenia Petre, Guido Masera

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29

GLVLSI
1996
IEEE

77views VLSI» more GLVLSI 1996»

A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization

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A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization

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Nelson L. Passos, Edwin Hsing-Mean Sha

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27

GLVLSI
1996
IEEE

91views VLSI» more GLVLSI 1996»

Macromodeling C- and RC-loaded CMOS inverters for timing analysis

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Macromodeling C- and RC-loaded CMOS inverters for timing analysis

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Ayman I. Kayssi

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20

GLVLSI
1996
IEEE

109views VLSI» more GLVLSI 1996»

Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs

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Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs

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Laura Heinrich-Litan, Paul Molitor, Dirk Möll...

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25

GLVLSI
1996
IEEE

96views VLSI» more GLVLSI 1996»

A Provably Good Moat Routing Algorithm

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A Provably Good Moat Routing Algorithm

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Joseph L. Ganley, James P. Cohoon

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28

GLVLSI
1996
IEEE

139views VLSI» more GLVLSI 1996»

Design and VLSI Implementation of a Unified Synapse-Neuron Architecture

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Design and VLSI Implementation of a Unified Synapse-Neuron Architecture

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Hormoz Djahanshahi, Majid Ahmadi, Graham A. Jullie...

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31

GLVLSI
1996
IEEE

115views VLSI» more GLVLSI 1996»

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh

14 years 3 months ago

A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh

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A VLSI implementation of a programmable router schemefor parallel interconnectionnetwork architectures is presented in this paper. The router executes routing

José G. Delgado-Frias, Jabulani Nyathi, Che...

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44

GLVLSI
1996
IEEE

145views VLSI» more GLVLSI 1996»

Boolean Function Representation Using Parallel-Access Diagrams

14 years 3 months ago

Boolean Function Representation Using Parallel-Access Diagrams

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Inthispaperweintroduceanondeterministiccounterpart to Reduced, Ordered Binary Decision Diagrams for the representation and manipulation of logic functions. ROBDDs are conceptually...

Valeria Bertacco, Maurizio Damiani

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17

GLVLSI
1996
IEEE

86views VLSI» more GLVLSI 1996»

A Reprogrammable FPGA-Based ATM Traffic Generator

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A Reprogrammable FPGA-Based ATM Traffic Generator

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Pong P. Chu

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