Sciweavers

FCCM
2002
IEEE
127views VLSI» more  FCCM 2002»
14 years 4 months ago
Hardware-Assisted Fast Routing
To fully realize the benefits of partial and rapid reconfiguration of field-programmable devices, we often need to dynamically schedule computing tasks and generate instance-sp...
André DeHon, Randy Huang, John Wawrzynek
FCCM
2002
IEEE
133views VLSI» more  FCCM 2002»
14 years 4 months ago
Reconfigurable Shape-Adaptive Template Matching Architectures
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...
Jörn Gause, Peter Y. K. Cheung, Wayne Luk
DFT
2002
IEEE
79views VLSI» more  DFT 2002»
14 years 4 months ago
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm
We propose an algorithm for gate-delay fault diagnosis. It is based on the inject-and-evaluate paradigm [1], in which the fault site(s) are predicted through a series of injection...
Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
14 years 4 months ago
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
Thomas Verdel, Yiorgos Makris
DFT
2002
IEEE
79views VLSI» more  DFT 2002»
14 years 4 months ago
Neural Networks-Based Parametric Testing of Analog IC
Viera Stopjaková, D. Micusík, Lubica...
DFT
2002
IEEE
117views VLSI» more  DFT 2002»
14 years 4 months ago
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
Ozgur Sinanoglu, Alex Orailoglu
DFT
2002
IEEE
115views VLSI» more  DFT 2002»
14 years 4 months ago
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis
IDDQ test loses its effectiveness for deep sub-micron chips since it cannot distinguish between faulty and fault-free currents. The concept of current ratios, in which the ratio o...
Sagar S. Sabade, D. M. H. Walker
DFT
2002
IEEE
127views VLSI» more  DFT 2002»
14 years 4 months ago
A New Functional Fault Model for FPGA Application-Oriented Testing
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo ...
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
14 years 4 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
DFT
2002
IEEE
102views VLSI» more  DFT 2002»
14 years 4 months ago
On-Chip Jitter Measurement for Phase Locked Loops
Tian Xia, Jien-Chung Lo