Sciweavers

HPCA
2005
IEEE
14 years 7 months ago
Multithreaded Value Prediction
This paper introduces a novel technique which leverages value prediction and multithreading on a simultaneous multithreading processor to achieve higher performance in a single th...
Nathan Tuck, Dean M. Tullsen
HPCA
2005
IEEE
14 years 7 months ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham
HPCA
2005
IEEE
14 years 7 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
HPCA
2005
IEEE
14 years 7 months ago
Improving Multiple-CMP Systems Using Token Coherence
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...
Michael R. Marty, Jesse D. Bingham, Mark D. Hill, ...
HPCA
2005
IEEE
14 years 7 months ago
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
Simultaneous multithreading (SMT) and chip multiprocessing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are s...
Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadro...
HPCA
2005
IEEE
14 years 7 months ago
Transition Phase Classification and Prediction
Most programs are repetitive, where similar behavior can be seen at different execution times. Proposed on-line systems automatically group these similar intervals of execution in...
Jeremy Lau, Stefan Schoenmackers, Brad Calder
HPCA
2005
IEEE
14 years 7 months ago
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs
Memory leaks and memory corruption are two major forms of software bugs that severely threaten system availability and security. According to the US-CERT Vulnerability Notes Datab...
Feng Qin, Shan Lu, Yuanyuan Zhou
HPCA
2005
IEEE
14 years 7 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
HPCA
2005
IEEE
14 years 7 months ago
Checkpointed Early Load Retirement
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...
Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jos...
HPCA
2005
IEEE
14 years 7 months ago
Software Directed Issue Queue Power Reduction
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
Antonio González, Jaume Abella, Michael F. ...