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    DAC
    2006
    ACM
    177views Computer Architecture» more  DAC 2006»
    Stochastic variational analysis of large power grids considering intra-die correlations
    15 years 12 days ago
    Stochastic variational analysis of large power grids considering intra-die correlations
    Download  www.public.asu.edu
    For statistical timing and power analysis that are very important problems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctua...
    Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhar...
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    DAC
    2006
    ACM
    123views Computer Architecture» more  DAC 2006»
    Games are up for DVFS
    15 years 12 days ago
    Games are up for DVFS
    Download  www.comp.nus.edu.sg
    Graphics-intensive computer games are no longer restricted to highperformance desktops, but are also available on a variety of portable devices ranging from notebooks to PDAs and ...
    Yan Gu, Samarjit Chakraborty, Wei Tsang Ooi
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    DAC
    2006
    ACM
    163views Computer Architecture» more  DAC 2006»
    Architecture-aware FPGA placement using metric embedding
    15 years 12 days ago
    Architecture-aware FPGA placement using metric embedding
    Download  www.ece.cmu.edu
    Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
    Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...
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    DAC
    2006
    ACM
    120views Computer Architecture» more  DAC 2006»
    A design approach for radiation-hard digital electronics
    15 years 12 days ago
    A design approach for radiation-hard digital electronics
    Download  cobweb.ecn.purdue.edu
    Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gw...
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    DAC
    2006
    ACM
    147views Computer Architecture» more  DAC 2006»
    Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
    15 years 12 days ago
    Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
    Download  people.cs.ubc.ca
    Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
    Xiushan Feng, Alan J. Hu
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    DAC
    2006
    ACM
    176views Computer Architecture» more  DAC 2006»
    Statistical logic cell delay analysis using a current-based model
    15 years 12 days ago
    Statistical logic cell delay analysis using a current-based model
    Download  homepages.cae.wisc.edu
    A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
    Hanif Fatemi, Shahin Nazarian, Massoud Pedram
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    DAC
    2006
    ACM
    100views Computer Architecture» more  DAC 2006»
    A parallelized way to provide data encryption and integrity checking on a processor-memory bus
    15 years 12 days ago
    A parallelized way to provide data encryption and integrity checking on a processor-memory bus
    Download  www.lirmm.fr
    This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...
    Reouven Elbaz, Lionel Torres, Gilles Sassatelli, P...
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    DAC
    2006
    ACM
    116views Computer Architecture» more  DAC 2006»
    Transistor abstraction for the functional verification of FPGAs
    15 years 12 days ago
    Transistor abstraction for the functional verification of FPGAs
    Download  www.altera.com
    or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
    Guy Dupenloup, Thierry Lemeunier, Roland Mayr
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    DAC
    2006
    ACM
    112views Computer Architecture» more  DAC 2006»
    A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
    15 years 12 days ago
    A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
    Download  www.ece.ucsb.edu
    Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
    Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
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    DAC
    2006
    ACM
    132views Computer Architecture» more  DAC 2006»
    Synthesis of synchronous elastic architectures
    15 years 12 days ago
    Synthesis of synchronous elastic architectures
    Download  www.lsi.upc.edu
    A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automat...
    Jordi Cortadella, Michael Kishinevsky, Bill Grundm...
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