ATS
2010
IEEE
13 years 10 months ago
2010
IEEE
One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and o...
ASPDAC
2010
ACM
13 years 10 months ago
2010
ACM
It is increasingly difficult to guarantee the first silicon success for complex integrated circuit (IC) designs. Post-silicon validation has thus become an essential step in the I...
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
DATE
2010
IEEE
14 years 5 months ago
2010
IEEE
—Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the ...
NOCS
2007
IEEE
14 years 6 months ago
2007
IEEE
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...
DATE
2007
IEEE
14 years 6 months ago
2007
IEEE
Network-on-Chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in gigascale integrated circuits. As traditional debug archi...
NOCS
2008
IEEE
14 years 6 months ago
2008
IEEE
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
DATE
2009
IEEE
14 years 6 months ago
2009
IEEE
—A large part of a modern SOC’s debug complexity resides in the interaction between the main system components. ion-level debug moves the abstraction level of the debug process...